A gated clock scheme controls the operating status of registers (i.e., flip-flops) that operate in synchronization with a clock signal. In the gated clock scheme, the supply of a clock signal to a flip-flop is suspended if the flip-flop is temporarily in such an operating status that no state transition should occur. This prevents the flip-flop from performing a data loading operation. With such control of a clock signal, needless power consumption is eliminated by suspending a data loading operation performed in synchronization with the clock signal.
FIG. 1 is a drawing showing an example of the configuration of a gated clock buffer. Gated clock buffers having the configuration as shown in FIG. 1 are instead along clock-signal supply paths as clock control elements. A gated clock buffer 10 includes a latch circuit 11 and an AND gate 12. The latch circuit 11 allows an input value into a control node EN to pass therethrough to appear as its output value during a period in which a clock signal CLK is 0 (LOW), and sustains an immediately preceding output value during a period in which the clock signal CLK is 1 (HIGH). The output of the latch circuit 11 is supplied to one input of the AND gate 12, and the other input of the AND gate 12 receives the clock signal CLK. The output of the AND gate 12 serves as a gated clock signal GCLK.
When an enable signal “1” applied to the control node EN is output from the latch circuit 11, the gated clock buffer 10 is in the enable state. In this enable state, the clock signal CLK supplied to the gated clock buffer 10 is output as the gated clock signal GCLK without any change. When an enable signal “0” applied to the control node EN is output from the latch circuit 11, the gated clock buffer 10 is in the disable state. In this disable state, the clock signal CLK supplied to the gated clock buffer 10 is blocked, so that the gated clock signal GCLK is fixed to 0. The control node EN of the gated clock buffer 10 is coupled to an output of a logic circuit that performs a logic operation (EN logic) for generating an enable signal.
In order to test a logic circuit in a system LSI that has no need to directly receive/transmit data from/to a device outside the chip, a scan test method is employed that receives/transmits serial data through a single terminal. In the scan test method, each flip-flop constituting the logic circuit has a scan input node and a scan output node. The scan output node of a given flip-flop is coupled to the scan input node of another flip-flop in such a manner that flip-flops are connected in cascade to constitute a flip-flop chain (i.e., scan chain). In a test operation mode, each scan flip-flop in the scan chain loads input data applied to its scan input node, and outputs the stored data from its scan output node in synchronization with a clock signal, in response to a signal indicative of a scan enable state applied from an external device.
An arrangement is typically made such that a clock signal is supplied to the flip-flops all the time during a scan test when a test is performed with respect to a semiconductor integrated circuit employing both the gated clock scheme and the scan test method. Specifically, a signal (e.g., test mode signal) that is kept to “1” all the time during a scan test may be used to fix to 1 the input signal into the control node EN of a gated clock buffer.
FIG. 2 is a drawing showing an example of the configuration in which a clock signal is supplied to flip-flops all the time during a scan test. In FIG. 2, the control node EN of the gated clock buffer 10 is connected to the output of an OR gate 20. The OR gate 20 receives, at its input nodes, a signal output from a logic circuit having EN logic 21 and a signal (e.g., test mode signal) that is kept to 1 all the time during a scan test. At the time of scan test, the output of the OR gate 20 is set to 1, so that the gated clock buffer 10 is kept in the enable state all the time, thereby constantly supplying a clock signal to flip-flops 23 and 24. Here, a flip-flop 22 is provided for the purpose of detecting a failure of the EN logic 21. A check is made as to whether a value stored in the flip-flop 22 is similar to an expected value of the output of the EN logic 21, thereby detecting a failure of the EN logic 21.
In the configuration shown in FIG. 2, there is no need to take into consideration the operation of the gated clock buffer when an automatic test pattern generator (ATPG) is used to generate test patterns for the semiconductor integrated circuit. Namely, test patterns may be generated by ignoring the presence of the gated clock buffer, which makes it easier to generate test patterns. In this case, however, it is not possible to detect a failure of the latch operation of the gated clock buffer by which the input of the latch circuit 11 passes through to appear as an output of the latch circuit 11 all the time. Further, since the input signal into the control node EN is fixed to 1, it is not possible to detect a stuck-at-1 fault and transition delay fault at the position of the control node EN. The term “stuck-at-1 fault” refers to a failure by which the node of interest is fixed to 1 (i.e., stuck at 1). The term “transition delay fault” refers to a failure by which transition timing at the node of interest is delayed to exceed a tolerable range.
Patent Document 1 discloses a configuration in which a signal equivalent to the input into the control node EN of the gated clock buffer shown in FIG. 2 is kept in the enable state all the time during a scan test. In the configuration disclosed in Patent Document 1, it is possible to detect a stuck-at-1 fault, but it is not possible to detect a transition delay fault. Analogous to the configuration shown in FIG. 2, this disclosed configuration may not detect a failure of the latch operation of a gated clock buffer. In this disclosed configuration, further, an existing flip-flop is utilized as an observation point in order to detect a failure of EN logic.
An existing technology for overcoming the problem that a stuck-at-1 fault and/or transition delay fault may not be detected controls an input into the control node EN of the gated clock buffer 10 by use of a scan shift mode signal during a scan test. The scan shift mode signal is set to the enable state (e.g., 1) during a scan shift operation in which scan flip-flops perform shift operations. The scan shift mode signal is set to the disable state (e.g., 0) during a capture operation in which the scan flip-flops load the data output from combinational logic circuits serving as user logics.
FIG. 3 is a drawing showing an example of the configuration in which the input into the control node EN is controlled by use of a scan shift mode signal. In FIG. 3, elements similar to those of FIG. 2 are referred to by similar numerals, and a description thereof will be omitted. In the configuration shown in FIG. 3, the OR gate 20 supplying its output to the control node EN of the gated clock buffer 10 receives a signal output from the logic circuit providing the EN logic 21 and a scan shift mode signal. At the time of a scan shift, the output of the OR gate 20 is set to 1, so that the gated clock buffer 10 is kept in the enable state all the time, thereby constantly supplying a clock signal to the flip-flops 23 and 24. At the time of a capture, the output of the OR gate 20 is set equal to the output of the EN logic 21, so that the enable/disable state of the gated clock buffer 10 is controlled in response to the output value of the EN logic 21.
In the configuration shown in FIG. 3, the enable/disable state of the gated clock buffer 10 is controlled according to the output value of the EN logic 21 during a capture operation, thereby making it possible to detect a stuck-at-1 fault and a transition delay fault. Specifically, the input-side flip-flops (not shown) of the EN logic 21 may be set to such values that the output of the EN logic 21 is set to 0. With this arrangement, the gated clock buffer 10 is placed in the disable state, thereby fixing the gated clock signal GCLK to 0. Further, the flip-flop 24, which is one of the flip-flops receiving the gated clock signal GCLK output from the gated clock buffer 10, is set to 1. Moreover, the data input supplied to the flip-flop 24 from a combinational circuit 25 is set to 0. Namely, an arrangement is made such that a value different from the current value of the flip-flop 24 is supplied as data input to the flip-flop 24.
In this state, one pulse of the clock signal CLK is supplied to the gated clock buffer 10. The gated clock buffer 10 may be in the disable state unless a stuck-at-1 fault exists at the control node EN. In this case, the gated clock signal GCLK is fixed to 0. No clock pulse is thus supplied to the flip-flop 24, and the content of the flip-flop 24 is kept to 1 without change. The gated clock buffer 10 may be in the enable state if a stuck-at-1 fault exists at the control node EN. In this case, clock pulses appear as the gated clock signal GCLK. A clock pulse is supplied to the flip-flop 24, and the content of the flip-flop 24 is changed from 1 to 0. Checking the stored value of the flip-flop 24 may determine whether a stuck-at-1 fault exists at the control node EN. Similarly, a transition delay fault may be detected by checking the stored value of the flip-flop 24.
In the configuration as shown in FIG. 3, there is a need to generate test patterns for detecting a stuck-at-1 fault at the time of test. This gives rise to a problem in that both the processing time of an automatic test pattern generator and the number of generated patterns increase. Analogous to the configuration shown in FIG. 2, further, it is not possible to detect a failure of the latch operation of the gated clock buffer by which the input of the latch circuit 11 passes through to appear as an output of the latch circuit 11 all the time.
Accordingly, there may be a need for a logic circuit that may detect a stuck-at-1 fault, a transition delay fault, a latch operation fault, and the like while suppressing an increase in the number of test patterns.
[Patent Document 1] Japanese Patent Application Publication No. 2002-323540